1. Field of the Invention
The present invention relates to a reduced pin (gigabit) media independent interface, and a method of forming such an interface. More particularly, the invention relates to signal encoding and decoding techniques for reducing interface pin count.
2. Background Information
Interconnections between computers, peripheral devices, and Internet appliances (referred to as network clients) are ubiquitous. With networks firmly established in everyday life, there is now more demand in the form of increased data transfer rate and functionality being placed on the network switches and other hardware which facilitate network communication to support more complex applications such as multimedia. As a result, the integrated circuits (ICs) in these components are becoming more highly integrated and complex to meet this demand. One problem is that added complexity tends to increase external connections or pin count.
Conventional networks may utilize twisted pair cable such as Category 5 and operate at a data rate of either 10 megabits per second (Mb/s) which generally complies with I.E.E.E. Standard 802.3, section 14, commonly known as 10BASE-T, and 100 Mb/s which generally complies with I.E.E.E. Standard 802.3, sections 24 and 25, commonly known as 100BASE-TX. With the demand for increased data transfer rates, a newer networking standard has been proposed that utilizes twisted pair cable and operates at a nominal data transfer rate of 1 gigabit (1000 megabits) per second. The 1 gigabit per second (Gb/s) transfer rate complies with I.E.E.E. Standard 802.3, section 40, commonly known as 1000BASE-T.
These two standards have different requirements and interfaces. When the network is operated in accordance with 10BASE-T or 100BASE-TX, the interface for interconnecting controllers and transceivers is defined in accordance with the a Media Independent Interface (MII). In either a 10BASE-T or a 100BASE-TX system, MII requires 16 connection lines or pins connecting the IC embodying the physical layers (PHY) to the IC embodying the media access controller layers (MAC). When the network is operated at a higher transmission rate in accordance with 1000BASE-T, the interface is defined by the Gigabit MII (GMII). Twenty-four connection lines or pins are required for 1000BASE-T.
The pin count problem in such systems becomes more apparent when we consider that a typical network switch has n ports, where n is the number of PHY and MAC layers respectively. Since the n MACs are typically fabricated as a single integrated circuit, the number of pins are 24×n. For example, if there are 24 ports then the n MACs requires 24×24 or 576 pins. A higher number of pins result in a larger die, a larger package, a more complicated integrated circuit and higher costs, particularly at the higher data transfer rates.
Various attempts have been made to solve the above-mentioned problem. Two ad hoc standards, namely Reduced Media Independent Interface (RMII) and Serial Media Independent Interface (SMII) reduce the number of pins by serialization techniques for 10BASE-T and 100BASE-TX. The RMII technique requires 7 pins per port and the frequency doubles from 25 MHz to 50 MHz. Thus, for a 24 port switch, 7×24 or 168 pins are required. The SMII technique requires 2 pins per port plus 1 synchronizing pin, and the frequency increases five fold from 25 MHz to 125 MHz. In the SMII technique, 2×24+1 or 49 pins are required. As will be appreciated by those of ordinary skill in the art, these techniques operate at frequencies in which clock recovery between the PHY and MAC layers is not required.
While RMII and SMII provide reduced pin count interfaces, they are only applicable to 10BASE-T and 100BASE-TX systems. Thus, there is a need for an effective interface that reduces pin or connection count in a 1000BASE-T system without compromising functionality, and that also has the flexibility to be used in 10BASE-T and 100BASE-TX systems as well.